Digital Electronics electronics engineering diploma 3rd semester

Digital Electronics  electronics engineering diploma 3rd semester

Government of Karnataka

Department of Technical Education Board of Technical Examinations, Bengaluru

Course Title	: Digital Electronics	Course Code	: 15EC32T
Semester	: Third	Credits	: 4
Teaching Scheme in Hrs (L:T:P) : 4:0:0		Course Group	: Core
Type of course	: Lecture	Total Contact Hours	: 52
CIE	: 25 Marks	SEE	: 100 Marks

  Prerequisites

Knowledge of basics of number systems and digital electronics.

  Course Objectives

1. Understand the working of various digital electronics circuits.

2. Apply principles of number systems and Boolean algebra to solve simple logical problems

3. Learn to design the simple digital circuits.

4. Enable to learn principles digital processors in higher learning

  Course Outcomes

On successful completion of the course, the students will be able to attain the following COs

Course Outcome		CL	Linked PO	Teaching Hrs
CO1	Apply the basic knowledge of digital electronics to construct and design simple combinational digital circuits.	R/U/A	1,2,3,4,10	09
CO2	Construct flip-flop circuits and analyze their functioning	R/U/A	1,2,3,4,10	09
CO3	Construct counters and shift registers and understand their operation.	R/U/A	1,2,3,4,10	10
CO4	Understand the functioning of A to D and D to A converters and their relevance.	R/U/A	1,2,3,4,10	09
CO5	Understand the function and applications of various types of memories and digital IC families.	R/U/A	1,2,3,4,10	09
CO6	Construct, analyze and verify the functioning of simple digital circuits/ICs using modern tools.	R/U/A	1,2,3,4,5,6,7, 10	06
Total				52

Course-PO attainment matrix

Course	Programme Outcomes
	1	2	3	4	5	6	7	8	9	10
Digital Electronics	3	3	3	3	1	1	1	--	--	3
Level 3- Highly Addressed, Level 2-Moderately Addressed, Level 1-Low Addressed. Method is to relate the level of PO with the number of hours devoted to the COs which address the given PO. If >40% of classroom sessions addressing a particular PO, it is considered that PO is addressed at Level 3 If 25 to 40% of classroom sessions addressing a particular PO, it is considered that PO is addressed at Level 2 If 5 to 25% of classroom sessions addressing a particular PO, it is considered that PO is addressed at Level 1 If < 5% of classroom sessions addressing a particular PO, it is considered that PO is considered not-addressed.

Course content and pattern of marks for SEE

Unit	Unit Name	Teaching Hours	Questions for SEE			Marks	Weightage (%)
			R	U	A
1	Combinational logic circuits	09	05	10	10	25	17
2	Basic sequential circuits	09	05	05	15	25	17
3	Registers and counters	10	05	10	15	30	20
4	D to A and A to D converters	09	05	10	10	25	17
5	Memories and programmable devices	09	05	10	10	25	17
6	Digital integrated circuits	06	05	05	05	15	12
Total		52	30	50	65	145	100

  Course Contents

Introduction: Combinational digital circuit. Multiplexers: definition, expression, truth-table, realization of simple (2:1) multiplexer using gates, and applications. Application of multiplexers to implement logic gates and simple sum-of-product equations, list of IC multiplexers and their features. Realization of higher-order multiplexer using lower-order multiplexer ICs. Demultiplexer: definition, expression, realization of simple (1:2) demultiplexer using gates, truth-table and applications, and list of IC demultiplexers and their features. Decoders and encoders: Definition and relevance of decoders and encoders. Logic diagram and truth-table of Decimal-to-BCD encoder and BCD-to-Decimal decoder. Identification of different decoder and encoder ICs. Need, logic diagram and truth table of BCD to 7-segment decoder. Concept and application of simple (maximum 4 bit) priority encoder.

 

 

Introduction to sequential circuits: Comparison of combinational and sequential circuits. Definition of clock and triggering, types of triggering and their symbolic representations in logic circuits/diagrams. Flip-flops: Operation, gate-level circuit, symbol, truth-table and timing wave- forms of clocked RS flip-flop and J-K flip-flop. Relevance of asynchronous inputs to flip-flops. Race-around problem and remedies, MS flip-flop, D and T flip-flop. Identify and list flip-flop ICs. Timer 555: Internal diagram of IC 555 and its application as astable and monostable multivibrators. Flip-flop as bistable multivibrator.

Registers: Classification of registers, realization of simple (3 or 4 bit) SISO, SIPO, PISO and PIPO using flip-flops, concept of universal shift-register. List shift-register ICs. Ring counter and Johnson’s counter: 3 bit circuit, truth-table and on applications. Counters: definition, modulus, classification (definitions of up/down, asynchronous/synchronous, full-mod/partial- mod) and applications. Working and realization (using flip-flops) of asynchronous and synchronous 3-bit or 4-bit counters, and their comparison. Realization of higher-mod counters using lower-mod counters. List counter ICs and study configuring IC 7490 as decade counter.

Data/signal conversion: Concept and need. DAC: Definition, symbolic representation, types, and applications. Circuit, functioning and output expression for 3 or 4-bit DAC using Resistive  divider and binary-ladder network. DAC specifications- resolution, accuracy, settling time, speed, linearity and monotonicity, and simple problems. Identify IC DACs and list their features. ADC: Definition, types, applications, specifications-resolution, accuracy, non-linearity, and conversion time. Working of 3-bit or 4-bit flash type, successive approximation and dual-slope ADCs, and simple problems. Identify IC ADCs and list their features.

Introduction: Definition and relevance of memories. Classification: Based on fabrication material, data retention, speed, storage capacity, cost and application. Working principle and features of magnetic memory, ROM, PROM, EPROM, E2PROM, flash memory, static and dynamic RAM cells, DDR memory & its variants and disk memories. Memory accessing process in semiconductor, magnetic and disk memories. Memory word-size and capacity of memories with examples. Programmable devices: Difference between fixed logic and programmable logic, PLA and PAL-architecture, and implementation of simple Boolean equations.

Logic families: Introduction, classification, definitions of fan-in, fan-out, propagation delay, power dissipation and noise margin. Working and circuit of standard TTL NAND gate and CMOS inverter, voltage levels in TTL and CMOS. Comparison of characteristics ECL, TTL, I2L and CMOS logic families. Interfacing of TTL and CMOS devices. Features of HMOS and CHMOS families. Concept of ESD and remedy.

 

  References

1. Digital principles and applications. Donald P Leach, Albert Paul Malvino, Goutam Saha, McGraw Hill Publisher, 8th edition, ISBN 10: 9339203402 ISBN 13: 9789339203405

2. Digital Systems-principles and applications. Ronald J. Tocci, Neal S.Widmer, Gregory L.Moss, 10th edition,ISBN : 0131725793

3. Digital Electronics –principles and integrated circuits. Anil K. Maini. Wiley publications,first edition . ISBN: 978-0-470-03214-5

4. Digital Computer Fundamentals,- Thomas C Bartee ,McGraw-Hill Publisher,6th edition.ISBN 10: 0070038996 / ISBN 13: 9780070038998

5. Digital fundamentals –Floyd and Jain, PEARSON EDUCATION publication, 8th Edition , ISBN-13: 978-0132359238 ,ISBN-10: 0132359235

6. www.nptel.ac.in

7. http://freevideolectures.com/Course/3164/Digital-Electronics

8. http://www.freebyte.com/electronics/

9. https://www.circuitlogix.com

10. http://www.vlab.co.in

11. www.electronics-tutorials.ws

12. http://www.allaboutcircuits.com

13. http://ocw.mit.edu/

  Course Delivery

The course will be delivered through lectures, presentations and support of modern tools. Student activities are off-class

  Course Assessment and Evaluation Scheme

  Master Scheme

Assessment Method	What		To Whom	Assessment mode /Frequency /timing	Max. Marks	Evidence Collected	Course Outcomes
Direct assessment	CIE	IA	Students	Three tests+	20	Blue Books	1 to 6
				Activity*	05	Activity Sheets	1 to 6
	SEE	End exam		End of the course	100	Answer Scripts at BTE	1 to 6
				Total	125
Indirect	Student feedback on course		Students	Middle of the Course	Nil	Feedback Forms	1 to 3 Delivery of course
	End of course survey			End of the Course	Nil	Question- naires	1 to 6 Effectiveness of delivery instructions & assessment methods

Legends: CIE-Continuous Internal Evaluation, SEE- Semester End-exam Evaluation

+ Every I.A. test shall be conducted for 20 marks. Average of three tests, by rounding off any fractional part thereof to next higher integer, shall be considered for IA.

 

*Students should do activity as per the list of suggested activities/ similar activities with prior approval of the teacher. Activity process must initiated well in advance so that it can be completed well before the end of the term.

Questions for CIE and SEE will be designed to evaluate the various CLs as per the weightage shown in the following table.

Sl. No.	Cognitive Levels (CL)	Weightage (%)
1	Remembering	20
2	Understanding	35
3	Applying	45
Total		100

(i) Student Activity (5 marks)

The following student activities or similar activities can be assigned for assessing CIE/IA marks

Sl. No.	Activity
1	Collect the information about the different types of display devices used in digital circuits and carry out a seminar
2	Collect the specification sheets, availability and cost of any two ADC and DAC ICs
3	Prepare a block diagram approach to construct a digital clock or a frequency counter or a digital voltmeter or any other similar digital electronic circuits and analyze the cost of the application
4	Prepare a note on E-waste and disposal of PCBs and ICs, carry out a seminar
5	Design and simulate the working of any simple logic circuit using a suitable modern software tool
Execution Notes: 1.     Maximum of 2 students in each batch for student activity 2.     Above activities may be distributed among different batches; activity No. 5 is mandatory and any one activity among 1 to4 or any similar activities per batch may be assigned by the teacher based on interest of the students. 3.     Project activities shall be carried out throughout the semester and present the project report at the end of the semester; concerned teacher is expected to observe and record the progress of students’ activities 4.     Submit qualitative hand-written report not exceeding 6 pages; one report per batch 5.     Each of the activity can be carried out off-class well in advance; however, demonstration/presentation should be done during laboratory sessions 6.     Assessment shall be based on quality of work as prescribed by the following rubrics table

(ii) Model of rubrics for assessing student activity (for every student)

Dimension	Scale					Marks (Example)
	1 Unsatisfactory	2 Developing	3 Satisfactory	4 Good	5 Exemplary
1. Research and gathering information	Does not collect information relate to topic	Collects very limited information, some relate to topic	Collects basic information, most refer to the topic	Collects more information, most refer to the topic	Collects a great deals of information, all refer to the topic	3
2. Full-fills team roles and duties	Does not perform any duties assigned to the team role	Performs very little duties	Performs nearly all duties	Performs almost all duties	Performs all duties of assigned team roles	2
3. Shares work equality	Always relies on others to do the work	Rarely does the assigned work, often needs reminding	Usually does the assigned work, rarely needs reminding	Always does the assigned work, rarely needs reminding.	Always does the assigned work, without needing reminding	5
4. Listen to other team mates	Is always talking, never allows anyone to else to speak	Usually does most of the talking, rarely allows others to speak	Listens, but sometimes talk too much,	Listens and talks a little more than needed.	Listens and talks a fare amount	3
Total marks						ceil(13/4)= 4

(i)       CIE/IA Tests (20 Marks)

Three tests have to be conducted, during specified schedule, in accordance with the test pattern given below and their average-marks shall be considered for CIE/IA.

(ii)     Format of CIE/IA test question paper

 

CIE Question Paper
Institution Name and Code
Course Coordinator/Teacher
Program Name			Test No.			Units
Class/Sem			Date			CL
Course Name			Time			COs
Course Code			Max. Marks			POs
Note to students: Answer all questions
Question No.	Question				Marks	CL		CO	PO
1
2
3
4

Legends: PO-Program Outcome, CO-Course outcome, CL-Cognitive Level, R-Remember, U-Understand, A-Apply

Note: Internal choice may be given in each CO at the same cognitive level (CL)

(v) Model question paper for CIE

CIE Question Paper
Institution Name and Code
Course Coordinator/ Teacher
Program Name		Electronics and Communication		Test No.	1		Units	1 & 2
Class/Sem		3rd Sem		Date	--/--/----		CL	R/U/A
Course Name		Digital Electronics		Time	10-11AM		COs	1 & 2
Course Code		15EC32T		Max. Marks	20		POs	1& 3
Note to students: Answer all questions
No.	Question					Marks	CL		CO	PO
1	Define a demultiplexer and construct a 1:4 demultiplexer using logic gates					05	R/A		1	1,2
2	Illustrate  use  of  multiplexer  to  realize  y=A̅B¯ C̅ +A̅B¯ C+ABC  OR Show how to realize 2-iput NOR gate using a multiplexer IC					05	A		1	1,2
3	Define combinational and sequential circuits and compare them					05	R/U		2	1,2
4	Identify the problems associated with JK flip-flop  and modify JK flip-flop or suggest remedy to overcome the problem OR Write the JK flip-flop gate-level diagram and convert it to D flip-flop					05	A/U		2	1,2

Semester End-exam Evaluation (SEE)

(i) End-exam question-paper pattern

Unit	Unit Name	Study Duration (Hrs.)	No. Questions for end-exam
			PART – A 5 Marks	PART – B 10 Marks
1	Combinational logic circuits	09	01	02
2	Flip-flops and related circuits	09	01	02
3	Registers and counters	10	02	02
4	D to A and A to D converters	09	01	02
5	Memory devices	09	03	01
6	Digital integrated circuits	06	01	01
	Total	52	09 (45 Marks)	10 (100 Marks)