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GOVERNMENT OF KARNATAKA DEPARTMENT OF TECHNICAL EDUCATION BOARD OF TECHNICAL EXAMINATIONS DIPLOMA ANNUAL (SUPPLY/SEMESTER SCHEME) THEORY   EXAMINATIONS -NOV   2011 DRAFT   TIME-TABLE COURSE    :           9ME        MECHANICAL ENGG. (GENERAL)                                   (NEW SCHEME) YR     SUB         QPCODE                                         SUBJECT NAME           ...

DEMORGAN’S FIRST THEOREM Demorgan’s first theorem stated as follows in words, The complement of a sum is equal to the individual components. SYMBOL: Demorgans first theorem symbol CIRCUIT DIAGRAM: Demorgans first therom circuit diagram BOOLEAN EXPRESSION:   boolean expression TRUTH TABLE: INPUT OUTPUT INPUT OUTPUT A B Y= A B Y= 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0

JK FLIP-FLOP Using a clock pulse to control the change of state of the flip-flop synchronizes its operation with the rest of th circuit.this avoids the “race condition” that can occur with the RS flip-flop. The device is triggered by the negative(falling) edge of yhe clock pulse. LOGIC SYMBOL: JK FLIP-FLOP SYMBOL Circuit diagram CIRCUIT DIAGRAM JK FLIP-FLOP TRUTH TABLE J K Q n-1 ACTION 0 0 Q n (no change) 0 1 0 Reset 1 0 1 Set 1 1 Q n toggle

XOR GATE If An Odd Number Of Inputs Is High, The Output Is High. Otherwise, The Output Is Low. SYMBOL: XOR GATE SYMBOL CIRCUIT DIAGRAM: CIRCUIT DIAGRAM XOR GATE Boolean expression: TRUTH TABLE: A B 0 0 0 0 1 1 1 0 1 1 1 0

XNOR GATE If an even number of inputs is high, the output is high. If an odd number of  inputs are high, the output is low. SYMBOL: Xnor gate symbol CIRCUIT DIAGRAM: Xnor gate circuit diagram Boolean expression : TRUTH TABLE: A B 0 0 1 0 1 0 1 0 0 1 1 1

SR-FLIP FLOP SYMBOL: SR FLIP FLOP[ SYMBOL DEFINATION:       The RS Flip-Flop Has An Undesired Operating Condition, Where 1 Level At Both Inputs Will Cause Both Outputs To Go To 0 Level. This Undefined Condition Must Be Avoided. Circuits Involving Feedback Ill Lead To A “Race Condition” Where The Output Will Be Unpredictable. CIRCUIT DIAGRAM:- SR FLIP FLOP CIRCUIT DIAGRAM TRUTH TABLE: S R Q      Staff 0 0 NC NC NO CHANGE 0 1 0 1 RESET 1 0 1 0 SET 1 1 1/0 1/0 FORBIDDENT STATE RS flip-flop are not suited for sequential circuits without additional circuitry. Alone they are used for debouncing switches and holding states, such a in alarm systems.

OR GATE If one or more inputs is high, the output is high. If all inputs are low, the output is low. Symbol: OR Gate symbol CIRCUIT DIAGRAM: OR Gate circuit diagram Boolean expression : Y=A+B TRUTH TABLE: A B Y=A+B 0 0 0 0 1 1 1 0 1 1 1 1

NOT GATE *If input is low then output is high otherwise input is high output is low.  *A NOT gate produces an output that is the complement of the four commonly used signal. *Only one input one output SYMBOL: NOT Gate symbol CIRCUIT DIAGRAM: Circuit diagram NOT Gate Boolean Expression : Y= TRUTH TABLE A Y= 0 1 1 0