DIPLOMA ANNUAL (SUPPLY/SEMESTER SCHEME) THEORY EXAMINATIONS -NOV 2011

GOVERNMENT OF KARNATAKA
DEPARTMENT OF TECHNICAL EDUCATION
BOARD OF TECHNICAL EXAMINATIONS
DIPLOMA ANNUAL (SUPPLY/SEMESTER SCHEME) THEORY   EXAMINATIONS -NOV   2011
DRAFT   TIME-TABLE
COURSE    :           9ME        MECHANICAL ENGG. (GENERAL)                                   (NEW SCHEME)

YR     SUB         QPCODE                                         SUBJECT NAME                                              DAY                DATE                        TIME


3       04           9ME34     MECHANICAL MEASURMENTS & METROLOGY                     FRI     9/12/2011                09 -         12

3       02           9ME32     FLUID MECHANICS & MACHINARY                                           MON    12/12/2011              09 -         12

4       01           9ME41     THEORY OF MACHINES                                                                     FRI     25/11/2011              14 -         17

4       02           9ME42     THERMAL ENGINEERING-I                                                             TUE    29/11/2011              14 -         17

4       03           9ME43     MANUFACTURING TECHNOLOGY-II                                            FRI     2/12/2011                14 -         17

4       04           9ME44     FLUID POWER ENGINEERING                                                        WED    7/12/2011                14 -         17

5       04           9ME54     MECHATRONICS                                                                                 SAT    26/11/2011              14 -         17

5       02           9ME52     THERMAL ENGINEERING-II                                                          MON    28/11/2011              14 -         17

5       01           9ME51     BASIC MGMT SKILL & INDIAN CONSTN                                   WED    30/11/2011              14 -         17

5       03           9ME53     D/N   OF MACHINE ELEMENTS                                                       SAT    3/12/2011                14 -         17


NOTE
THIS IS ONLY A DRAFT COPY. AFTER CORRECTION   (IF ANY) FINAL COPY WILL BE ANNOUNCED ON 05/11/2011
Page 161 of 198



Source:http://dte.kar.nic.in

DEMORGAN'S FIRST THEOREM

DEMORGAN’S FIRST THEOREM
Demorgan’s first theorem stated as follows in words, The complement of a sum is equal to the individual components.
SYMBOL:
Demorgans first theorem symbol

CIRCUIT DIAGRAM:
Demorgans first therom circuit diagram

BOOLEAN EXPRESSION:  
boolean expression


TRUTH TABLE:
INPUT
OUTPUT

INPUT
OUTPUT
A
B
Y=
A
B
Y=
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
0


JK FLIP-FLOP

JK FLIP-FLOP
Using a clock pulse to control the change of state of the flip-flop synchronizes its operation with the rest of th circuit.this avoids the “race condition” that can occur with the RS flip-flop. The device is triggered by the negative(falling) edge of yhe clock pulse.

LOGIC SYMBOL:
JK FLIP-FLOP SYMBOL
Circuit diagram
CIRCUIT DIAGRAM JK FLIP-FLOP

TRUTH TABLE
J
K
Qn-1
ACTION
0
0
Qn
(no change)
0
1
0
Reset
1
0
1
Set
1
1
Qn
toggle


XOR GATE

XOR GATE
If An Odd Number Of Inputs Is High, The Output Is High. Otherwise, The Output Is Low.
SYMBOL:
XOR GATE SYMBOL
CIRCUIT DIAGRAM:
CIRCUIT DIAGRAM XOR GATE
Boolean expression:

TRUTH TABLE:
A
B
0
0
0
0
1
1
1
0
1
1
1
0


XNOR GATE

XNOR GATE
If an even number of inputs is high, the output is high. If an odd number of  inputs are high, the output is low.
SYMBOL:
Xnor gate symbol
CIRCUIT DIAGRAM:
Xnor gate circuit diagram
Boolean expression :
TRUTH TABLE:
A
B
0
0
1
0
1
0
1
0
0
1
1
1



SR-FLIP FLOP

SR-FLIP FLOP
SYMBOL:
SR FLIP FLOP[ SYMBOL

DEFINATION:
      The RS Flip-Flop Has An Undesired Operating Condition, Where 1 Level At Both Inputs Will Cause Both Outputs To Go To 0 Level. This Undefined Condition Must Be Avoided. Circuits Involving Feedback Ill Lead To A “Race Condition” Where The Output Will Be Unpredictable.

CIRCUIT DIAGRAM:-
SR FLIP FLOP CIRCUIT DIAGRAM

TRUTH TABLE:
S
R
Q
    
Staff
0
0
NC
NC
NO CHANGE
0
1
0
1
RESET
1
0
1
0
SET
1
1
1/0
1/0
FORBIDDENT STATE

RS flip-flop are not suited for sequential circuits without additional circuitry. Alone they are used for debouncing switches and holding states, such a in alarm systems.

OR GATE

OR GATE
If one or more inputs is high, the output is high. If all inputs are low, the output is low.
Symbol:
OR Gate symbol

CIRCUIT DIAGRAM:
OR Gate circuit diagram

Boolean expression : Y=A+B

TRUTH TABLE:
A
B
Y=A+B
0
0
0
0
1
1
1
0
1
1
1
1


NOT GATE

NOT GATE
*If input is low then output is high otherwise input is high output is low.
 *A NOT gate produces an output that is the complement of the four commonly used signal.
*Only one input one output


SYMBOL:

NOT Gate symbol
CIRCUIT DIAGRAM:

Circuit diagram NOT Gate


Boolean Expression : Y=

TRUTH TABLE
A
Y=
0
1
1
0


NOR GATE

NOR GATE
If all inputs are low, the output is high.otherwise the output is low.
SYMBOL:

NOR Gate symbol

CIRCUIT DIAGRAM:
Nor gate circuit diagram
Boolean expression Y=A+B

TRUTH TABLE
A
B
Y=A+B
0
0
1
0
1
0
1
0
0
1
1
0

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